FIG. 3 shows a circuit construction of a prior art random access memory device (hereinafter referred to as "RAM"). In this device there are provided a plurality of memory cell columns each having a lurality of MOSTs, two dummy cells, an address decoder and dummy decoder for selecting a memory cell and dummy memory cell, respectively, a plurality of sense amplifiers for amplifying data read out from the memory cells, precharging and voltage balancing circuits for the bit lines, and pull down circuits for word lines.
In FIG. 3, the reference numerals 1al to 1an and 1bl to 1bn designate one bit memory cells, which store data of logical value "1" or "0". The reference numerals 1cl to 1cn and 1dl to 1dn designate one bit dummy cells, the reference numerals 41 to 4n and 51 to 5n designate bit lines for transmitting memory cell data, and these bit lines 41 to 4n and 51 to 5n transmit complementary data. The reference numerals 6a and 6b designate word lines to which signal .phi.w for driving a memory cell is supplied. The reference numerals 6c and 6d designate dummy word lines to which signal .phi.w for driving a dummy cell is also supplied.
The reference numerals 2al to 2an and 2bl to 2bn designate memory capacitances for storing memory cell data one end of which are connected to the nodes 3al to 3an and 3bl to 3bn and the other end of which are connected to ground. The reference numerals 2cl to 2cn and 2dl to 2dn designate dummy capacitances which have about half the capacitance value of those of the memory cells 2al to 2an and 2bl to 2bn. One end thereof are connected to the nodes 3cl to 3cn and 3dl to 3dn, and the other ends thereof are connected to ground. These dummy capacitances function to supply a reference voltage at the reading out of memory cell data. The reference numerals 7al to 7an and 7bl to 7bn designate switching MOSTs one main electrode of which are respectively connected to the nodes 3al to 3an and 3 bl to 3bn. The other main electrodes thereof are respectively connected to the bit lines 41 to 4n and 51 to 5n, and the gate electrodes thereof are respectively connected to the nodes 10al to 10an and 10bl to 10bn on the word lines. These switching MOSTs function to read out, to write in, or to hold the data of memory capacitances 2al to 2an, 2bl to 2bn.
The reference numerals 7cl to 7cn and 7dl to 7dn designate switching MOSTs one main electrode of which are respectively connected to the nodes 3cl to 3cn and 3dl to 3dn. The other main electrodes thereof are respectively connected to the bit lines 41 to 4n and 51 to 5n, and the gate electrodes thereof are respectively connected to the nodes on the dummy word lines 10cl to 10cn and 10dl to 10dn. These switching MOSTs function to read out the reference data from the dummy capacitances 2cl to 2cn and 2dl to 2dn. The reference numerals 29cl to 29cn and 29dl to 29dn designate MOSTs whose one main electrode of which are respectively connected to the nodes 3cl to 3cn and 3dl to 3dn. The other main electrodes thereof are connected to the ground, and the gate electrodes thereof are connected to the terminal 27 to which clock signal .phi..sub.D is supplied. These MOSTs function to provide for the next read out operation by setting the level of dummy capacitance to "0" in the waiting state of the RAM.
The reference numerals 8al to 8an and 8bl to 8bn designate parasitic resistances of the word lines one end of which are respectively connected to the nodes 10al to 10an and 10bl to 10bn, and the other ends thereof are respectively connected to the nodes 9al to 9an and 9bl to 9bn. These resistances are usually accompanied within a circuit wherein a lot of pairs of bit lines each pair being connected to the same sense amplifier 241 to 24n are arranged in parallel with each other as shown in FIG. 3. It is sufficient to use, a double layer wiring technique using aluminum having a low resistance value so as to reduce the above-described resistances. However, this technique is not generally used due to an increase in production process steps and reduction in reliability in second aluminum wiring. Thus, a high melting point metal such as polysilicon having relatively large resistance is commonly used in view of easiness in production.
The reference numerals 8cl to 8cn and 8dl to 8dn designate parasitic resistances of the dummy word lines one end of which are respectively connected to the nodes 10cl to 10cn and 10dl to 10dn, and the other ends thereof are respectively connected to the nodes 9cl to 9cn and 9dl to 9dn.
The reference numerals llal to llan and llbl to llbn designate parasitic capacitances of the word lines one end of which are respectively connected to the nodes 9al to 9an and 9bl to 9bn, and the other ends thereof are connected to ground.
The reference numerals llcl to llcn and lldl to lldn designate parasitic capacitances of the dummy word lines one end of which are respectively connected to the nodes 9cl to 9cn and 9dl to 9dn, and the other ends thereof are connected to ground.
The reference numerals 111 to lln and 121 to 12n designate bit line charging MOSTs provided between the bit lines 41 to 4n and 51 to 5n and the power supply terminal 19 (voltage V), respectively, and the gate electrodes thereof are connected to the nodes 141 to 14n, respectively. P channel MOSTs are used for these MOSTs, which are of reverse conductivity types to the MOSTs used for memory cells.
The reference numerals 131 to 13n designate bit line voltage balancing MOSTs which are provided between respective pairs of bit lines 41 to 4n and 51 to 5n, and the gate electrodes thereof are connected to the nodes 141 to 14n. P channel MOSTs are also used for these MOSTs. The nodes 141 to 14n are connected to the terminal 22 to which clock signal .phi..sub.E is supplied.
The reference numerals 241 to 24n designate sense amplifier circuits which are connected to respective pairs of bit lines and the terminals 251 to 25n to which clock signal .phi..sub.S is supplied, and these sense amplifier circuits function to amplify a micro voltage difference appearing between respective pairs of bit lines.
The reference numerals 301 to 30n designate MOSTs provided between the bit lines 41 to 4n and nodes 251 to 25n, respectively, and the gate electrodes thereof are connected to the bit lines 51 to 5n, respectively. Furthermore, the reference numerals 311 to 31n designate MOSTs provided between the bit lines 51 to 5n and nodes 251 to 25n, respectively, and the gate electrodes thereof are connected to the bit lines 41 to 4n, respectively.
These MOSTs 301 to 30n and 311 to 31n are connected in a cross coupled configuration to constitute a flip-flop circuit.
The reference numeral 33 designates a MOST provided between the power supply terminal 19 and node 35, and the gate electrode thereof is connected to a terminal 36 to which clock signal .phi..sub.S is supplied. The reference numeral 34 designates a MOST which is provided between a node 35 and ground, and the gate electrode thereof is connected to a terminal 37 to which clock signal .phi..sub.SO is supplied. The reference numeral 32 designates a MOST for driving the sense amplifiers 241 to 24n provided between the nodes 251 to 25n and ground, and the gate electrode thereof is connected to the node 35.
The reference numeral 21a designates a decoder circuit for decoding address signals Axl, Axl . . . Axn, Axn which are supplied from terminals 18a and outputting a voltage to one of outputs 16a, 16b . . . . To this decoder circuit the power supply voltage V and clock signal .phi..sub.P are supplied from terminals 19 and 20, respectively.
The reference numeral 21b designates a dummy decoder circuit for decoding the LSB of the column address Axl, Axl which are supplied from a terminal 18b and outputting a voltage to one of outputs 16c and 16d, and to this dummy decoder circuit the power supply voltage V and clock signal .phi..sub.P are supplied from the terminals 19 and 20, respectively. The reference numerals 15a and 15b designate MOSTs for connecting the word line driving signal .phi..sub.W which is supplied to the terminal 17 to the word line in accordance with the levels of outputs 16a and 16b of decoder circuit 21a. The reference numerals 15c and 15d designate MOSTs for connecting the word line driving signal .phi..sub.W which is supplied to the terminal 17 to the dummy word line in accordance with the levels of outputs 16c and 16d of dummy decoder circuit 21b. The reference numerals 23a and 23b designate MOSTs provided between the nodes at one end of word lines 28a and 28b and the ground, and the gate electrodes thereof are connected to the terminal 26 to which clock signal .phi..sub.C is supplied, and these MOSTs function to reduce noise voltages of the unselected word lines.
The reference numerals 23c and 23d designate MOSTs provided between the nodes 28c and 28d at one end of dummy word lines and ground, and the gate electrodes thereof are connected to the terminal 26 to which clock signal .phi..sub.C is supplied, and they function to reduce noise voltages of the unselected dummy word lines.
The circuit operation of FIG. 3 will be described with reference to FIG. 4. FIG. 4 shows the circuit operation while reading out data from the memory cells 1a.sub.l to 1a.sub.n. In this figure it is assumed that "0" data is stored in each memory cell.
Until time t.sub.0 all the outputs 16a, 16b . . . of decoder 21a are precharged to "1" by the clock signal .phi..sub.P, and the outputs 16c, 16d of dummy decoder 21b are also precharged to "1". The bit lines 41 to 4n and 51 to 5n are also precharged to the power supply voltage V by the clock signal .phi..sub.E. All the word lines and dummy word lines have the level "0" of clock signal .phi..sub.W, and these word lines are in "0" state while the MOSTs 15a, 15b . . . 15c, 15d are all turned on, and all the memory cells and dummy cells are in unselected states. The MOSTs 23a, 23b . . . , 23c, 23d are all turned on due to the clock signal .phi..sub.C being "1", whereby the word lines and dummy word lines are strongly fixed at "0". When the clock signal .phi..sub.P becomes "0" at time t.sub.0, the precharging of the decoder and dummy decoder is finished. Next, when address signals are applied to terminals 18a at time t.sub.1 the outputs 16a, 16b . . . of decoder 21a are all "0" except for one.
Hereinafter, it is assumed that only the output 16a are "1" and that the other outputs become all "0".
On this assumption, only the MOST 15a is turned ON, and the memory cells 1al to 1an connected to the left side bit lines 41 to 4n of bit line pairs, respectively, are selected by the clock signal .phi..sub.W. Then, the dummy decoder functions to select the dummy cells 1dl to 1dn which are connected to the right side 16d "1". After the selections by the decoder and by the dummy decoder are completed, the clock signal .phi..sub.E becomes V at time t.sub.2. Thus the MOSTs 111 to lln and 121 to 12n and 131 to 13n are turned OFF, the bit lines are at a high impedance state, and the device enters a waiting state for reading out of cell data. At the same time the clock signal .phi..sub.C comes to have a value which is slightly higher than the threshold voltage V.sub.TH of MOSTs 23a to 23d, and the word lines except for the word line 6a and dummy word line 6d are grounded to "0" with a relatively high resistance.
Next, the clock signal .phi..sub.W starts to rise up at time t.sub.3, and it reaches a final level V at time t.sub.4. Thus the voltages of the word line 6a and dummy word line 6d rise up, but the time periods required for rising up are different depending on the positions on the word lines. That is, at the nodes 10al and 10dl in the neighborhood of input point of clock signal .phi..sub.W the voltages of word lines rise up faster, but at the far side nodes 10an and 10dn the voltages of word lines rise up slowly. This is caused by parasitic resistances and capacitances accompanying the word lines and dummy word lines. Usually this delay is about 20 ns in the case of a 256 K bit RAM. In other words, the nodes 10al and 10dl rise up to the power supply voltage V at the same time t.sub.4 as that of the clock signal .phi..sub.W, the nodes 10an and 10dn reaches the power supply voltage V at time t.sub.5 which is about 20 ns after time t.sub.4. As the voltages of nodes 10al to 10an and 10dl to 10dn rise up the MOSTs 7al to 7an and 7dl to 7dn are turned ON, and the memory cell data and reference data are read out to the bit lines.
In this case as "0" data is stored in each memory cell the voltages of bit lines 41 to 4n are lowered. On the other hand, at the sides of bit lines 51 to 5n the reference data is read out from the dummy cell, whereby the voltages of bit lines 51 to 5n are lowered. However, the levels of bit lines 51 to 5n are higher than those of bit lines 41 to 4n. This is because the dummy cell capacitances are set at about half the capacitance of the memory cell capacitances as described above. Directly before time t.sub.5 the clock signal .phi..sub.S rises up from 0 to V, thereby turning ON the MOST 33. Then, as the clock .phi..sub.S0 is "0" the MOST 34 is in OFF state.
By the turning ON of the MOST 33 the gate voltage of the MOST 32 rises up thereby to turn ON the MOST 32, and the signal .phi..sub.S, that is, the voltages of nodes 251 to 25n start to be lowered (time t.sub.5). When the clock signal .phi..sub.S falls down the micro voltage differences between the bit lines 41 to 4n and bit lines 51 to 5n are amplified by the sense amplifiers 241 to 24n. At time t.sub.6 when the falling of clock signal .phi..sub.S is completed the voltages of bit lines 41 to 4n become "0" and the bit lines 51 to 5n become levels slightly lower than V, completing the amplification. This large voltage difference is transmitted to the latter stage circuit (not shown), and read out to the output of the RAM.
When the above-described reading out operation is completed, it is necessary to transit to a waiting state for reading out of the other memory cells. When transiting to the waiting state the voltage levels of memory cell capacitances are desirable to be perfect "0" or "1" level. When deviated from a complete level, the read out margin at the next read out operation is reduced. In order to satisfy this condition the MOSTs 301 to 30n and MOST 32 must be turned ON and the voltages of bit lines 41 to 4n must be fixed to the low impedance state of "0" until the voltage of word line 6a become 0 and MOSTs 7al to 7an are turned OFF. Furthermore, in order to avoid dead power consumption the MOST 32 must be turned OFF at the balanced state of the bit line voltage.
The operation waveforms while transiting to a waiting state after time t.sub.7 are shown in FIG. 4.
At time t.sub.7 the clock .phi..sub.W starts to fall and it reaches the final level "0" at time t.sub.8. Thus the voltages of the word line 6a and dummy word line also fall, and the times of falling are different dependent on the positions on the word line similarly as in cases of rising up. That is, at the nodes 10an, 10dn the falling down is slow and at the nodes 10al, 10dl it is fast. Herein, in order for the MOST 7an to enter a waiting state the gate voltage thereof is required to be a level lower than the threshold voltage V TH and it is turned OFF. Accordingly, the MOST 7an enters a waiting state approximately at time t.sub.9.
After the MOST 7an is turned OFF the clock .phi..sub.S0 becomes "1" thereby to turn ON the MOST 34 and to make the level of node 35 "0", whereby the MOST 32 is turned OFF. Next, at time t.sub.9 the clock .phi..sub.E starts to fall, and the balancing and precharging of bit line voltage starts at that time. Thus, the MOSTs 111 to 11n, 121 to 12n, and 131 to 13n are turned ON, thereby making the voltages of bit lines 41 to 4n rise up and the voltages of bit lines 51 to 5n start to fall transitorily. They rise up to the power supply voltage V at time t.sub.11, and the voltages of bit lines become approximately equalized levels (Theoretically it requires an infinite time for the voltages to be completely equalized to each other). When the balancing is insufficient and the voltage difference between a pair of bit lines is large the read out voltage margin at the next read out operation is lowered, thereby causing a malfunction.
Besides, at a time close to time t.sub.9 there occur rising up of clocks .phi..sub.P, .phi..sub.C and falling of the column address Ax1, Ax1, . . . . . . , Axn, Axn. However, these have no direct relation to the present invention.
As described above, the balancing of the bit line voltage must be conducted as soon as possible so as to enable a large read out margin at the next read out operation. Accordingly, it is most effective to conduct the balancing of the bit line voltage directly after the turning OFF of the memory cell switching MOST.
In the above-described prior art device the start timing of balancing, that is, the generation timing of clock .phi..sub.E is determined by a delay circuit comprising a cascade connection of MOST inverter circuits having clock signal .phi..sub.W as a reference. In this prior art device a resistor comprising a relatively high resistance, high melting point metal is used for the word line while such a resistor is not used in the above-described delay circuit.
In a case where the resistance of the resistor used for a word line becomes high dependent on variation in production the falling time becomes longer as shown by dotted lines of 10an, and the time required for turning OFF the switching MOST of a memory cell becomes long (time t.sub.10). When the balancing of bit lines is started in this state at time t.sub.9, the voltage of bit line 4n starts to rise up before the switching MOST becomes OFF. This causes entering of a high voltage into the memory cell 1an, which results in a malfunction.
In the prior art device of such a construction the variation of the resistance in production is presumed to be one obtained from calculation, and the start timing of the bit line voltage balancing is delayed over a period longer than required for the sake of safety. Thus the operation, cycle time of RAM (from time t.sub.0 to t.sub.0 ' in FIG. 2) is lengthened.